The present invention relates to a system and a method for displaying a color picture, in which primary color signals are converted into a field sequential signal, monochromatic pictures are sequentially displayed on a display screen of a monochromatic picture display device such as a monochromatic CRT, and light from the display screen passes through a coloring device such as a rotary color filter to provide a color picture display.
A prior art system for displaying a color picture is disclosed, for example, in Japanese Patent Kokai Publication Nos. 161383/1994. In the publication, a color picture signal for one frame is delivered as a field sequential signal RGB, which is a serial signal having a rate three times higher than the original signal. Specifically, the monochromatic picture is displayed in the sequence of the primary signals of R (odd field), G (odd field), B (odd field), R (even field), G (even field) and B (even field), and the vertical deflection for the green color G is shifted by one-half the horizontal scan period H (i.e., H/2) in opposite directions between the odd field and the even field.
FIG. 22 is a block diagram schematically showing a construction of the above-mentioned prior art system.
Referring to FIG. 22, the system has a field sequential signal generator 1, a reference clock generator 2 which generates a reference clock, a monochromatic picture display device 4 which displays a monochromatic picture in response to a field sequential signal RGB delivered from the field sequential signal generator 1, a coloring device 5 which colors the light emitted from the monochromatic picture displayed on the display screen of the monochromatic picture display device 4, and a controller 19 which controls the various components mentioned above.
FIG. 23 is a block diagram schematically showing a construction of the field sequential signal generator 1 of FIG. 22.
Referring to FIG. 23, the field sequential signal generator 1 has a storage section 10 and a switching section 9.
The storage section 10 has A/D converters 6R1, 6R2, 6G1, 6G2, 6B1 and 6B2 which convert inputted primary color signals R, G and B into digital data respectively, memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2 which store data delivered from the A/D converters 6R1, 6R2, 6G1, 6G2, 6B1 and 6B2 respectively, and D/A converters 8R1, 8R2, 8G1, 8G2, 8B1 and 8B2 which convert data read out from the memories 7R1, 7R2, 7G1, 7G2, 7Bl and 7B2 into analog signals respectively. A customary single board memory incapable of permitting a simultaneous write-in and read-out is used for each of the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2.
The switching section 9 selects one of outputs from the D/A converters 8R1, 8R2, 8G1, 8G2, 8B1 and 8B2 of the storage section 10.
FIG. 24 is a block diagram schematically showing a construction of the controller 19 shown in FIG. 22.
Referring to FIG. 24, the controller 19 has a horizontal frequency converter 11 which simply converts a horizontal sync signal HD into a triple rate horizontal sync signal 3H, and a vertical frequency converter 12 which simply converts a vertical sync signal VD into a triple rate vertical sync signal 3V. The controller 19 also has a write-in control circuit 13 which controls a write-in operation of data into memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2 of the storage section 10 of the field sequential signal generator 1, and a read-out control circuit 14 which controls a read-out operation of data from the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2. Additionally, the controller 19 has a display control circuit 15 which controls the monochromatic picture display device 4, a coloring control circuit 16 which controls the coloring device 5, a field discriminator 17 which discriminates a field into which a picture signal is to be written into, and a shift signal generator circuit 18 which generates a signal to shift the deflection up and down in the vertical direction.
The field discriminator 17 discriminates a particular memory into which the data is written and a particular field of one frame from which the data is derived, and also discriminates a particular field from which data is read out. This allows data to be read out from the same field in succession, and also allows the data to be read out in synchronism with the vertical sync signal.
FIG. 25 shows the monochromatic picture display device 4 shown in FIG. 22.
Referring to FIG. 25, the monochromatic picture display device 4 which is used to display the picture based on the field sequential signal RGB has a monochrome CRT 21 and a deflection control circuit 22.
FIG. 26 is a block diagram schematically showing the deflection control circuit 22 shown in FIG. 25 in detail.
Referring to FIG. 26, the deflection control circuit 22 has a vertical deflection shift circuit 23, a vertical deflection circuit 24, and a horizontal deflection circuit 25. A combination of the vertical deflection shift circuit 23 and the vertical deflection circuit 24 is effective to produce a vertical deflection pulse VP on the basis of a vertical control signal VS (i.e., 3VD) having a triple rate delivered from the display control circuit 15 of the controller 19. The horizontal deflection circuit 25 is effective to produce a horizontal deflection pulse HP on the basis of a horizontal control signal HS (i.e., 3 HD) having a triple rate delivered from the display control circuit 15 of the controller 19. Both of these pulses are effective to control the deflection of an electron beam in the monochromatic CRT 21.
FIG. 27 is a schematic view of a coloring device of FIG. 22.
Referring to FIG. 27, the coloring device 5 has a rotary color filter 28 having three filter sections corresponding to three primary colors R, G and B, a motor 27 which rotates the rotary color filter 28, and a motor control circuit 26 which delivers a motor control signal MS which is applied to the motor 27 on the basis of a coloring control signal CS delivered from the controller 19. The rotary color filter 28 is controlled so that it rotates in synchronism with a field sequential signal RGB in front of the display screen of the monochromatic CRT 21 in the monochromatic picture display device 4 in response to a signal from the controller 19 so that when a monochromatic picture is displayed on the monochromatic CRT 21, a filter section having a color which corresponds to the primary colors of the picture signals being displayed is located in front of the display screen.
FIGS. 28A and 28B are explanatory diagrams showing different television scanning schemes. FIG. 28A illustrates an interlace scanning in which two fields constitute a frame. In FIG. 28A, scanning lines in an odd field are shown by solid lines, while scanning lines in an even field are shown by broken lines. FIG. 28B illustrates a non-interlace scanning in which the scanning are conducted in the sequence of an arrangement of the scanning lines.
FIGS. 29A and 29B are explanatory diagrams illustrating the interlace scanning. In FIGS. 29A and 29B, an NTSC signal is chosen as an example of television signal. In FIG. 29A, scanning lines in a first field are shown by solid lines, while in FIG. 29B, scanning lines in a second field are shown by broken lines.
FIG. 30 is an explanatory diagram showing the timings of various signals and the position of the scanning lines which appear on the monochromatic picture display device 4 when the vertical correction pulse SS is not inputted to the vertical deflection shift circuit 23 of FIG. 26, and FIG. 31 an explanatory diagram showing the vertical deflection pulses VP and the position of scanning lines which appear on the monochromatic picture display device 4, when the vertical correction pulse SS is not inputted to the vertical deflection shift circuit 23.
FIG. 32 is an explanatory diagram showing the timings of various signals and the position of the scanning lines which appear on the monochromatic picture display device 4, when the vertical correction pulse SS is inputted to the vertical deflection shift circuit 23, and FIG. 33 is an explanatory diagram showing the vertical deflection pulse and the position of the scanning lines which appear on the monochromatic picture display device 4, when the vertical correction pulse SS is inputted to the vertical deflection shift circuit 23.
The operation of the prior art picture display mentioned above will now be described. Referring to FIG. 22, the three primary color signals R, G and B which are separated from a television signal are inputted to the field sequential signal generator 1, and are then stored in the storage section 10 shown in FIG. 23 on the basis of write-in control signals W and W' and a clock ADC which are supplied from the controller 19. Within the storage section 10, the individual primary color signals R, G and B are converted into digital data in the different A/D converters 6R1, 6R2, 6G1, 6G2, 6B1 and 6B2, respectively, in synchronism with the clock ADC. The converted digital data are written into the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2 for storage on the basis of write-in control signals W and W' associated with these memories and the clock ADC.
Subsequently, data is read out from the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2 on the basis of read-out control signals R and R' and a memory read-out clock DAC which has a triple rate as compared with the write-in clock. The D/A converters 8R1, 8R2, 8G1, 8G2, 8B1 and 8B2 convert digital data which is delivered from the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2 into a corresponding analog signal using the clock DAC associated with the D/A converters 8R1, 8R2, 8G1, 8G2, 8B1 and 8B2. The field sequential signal generator 1 stores a picture data for one field in each of the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2. Specifically, the storage section 10 includes memories 7R1, 7G1 and 7B1 for the primary color signals of one field, and memories 7R2, 7G2 and 7B2 for the primary color signals of the other field so that the primary color signals for two fields can be stored. The memories 7R1, 7G1 and 7B1, and the memories 7R2, 7G2 and 7B2 alternately store the primary color signals for one field, and the combination of all these memories store one frame, namely, two fields. It is to be noted that during the time the data is read out from the memories 7R1, 7G1 and 7B1, the data is written into the remaining memories 7R2, 7G2 and 7B2.
Referring to FIG. 24, the controller 19 receives the reference clock signal CK delivered from the reference clock generator 2, the vertical sync signal VD and the horizontal sync signal HD, and delivers several control signals which control the memories 7R1, 7R2, 7G1, 7G2, 7B1 and 7B2. The reference clock generator 2 delivers the clock CK which is synchronized with the horizontal sync signal HD. In response to the horizontal sync signal HD and the vertical sync signal VD, the write-in control circuit 13 delivers write-in control signals W and W' which are synchronized with the clock CK, and a write-in clock ADC having a frequency which is one-third the frequency of the clock CK. In response to the signal 3H which is obtained by converting the horizontal sync signal HD into a signal having a triple frequency in the horizontal frequency converter 11 (and thus a pulse-like signal having a width narrower than that of the horizontal sync signal HD) and the signal 3V which is obtained by converting the vertical sync signal VD into a signal having a triple frequency in the vertical frequency converter circuit 12 (and which is thus pulse-like signal having a width narrower than that of the vertical sync signal VD), the read-out control circuit 14 delivers the read-out control signals R and R' which are synchronized with the clock CK and a read-out clock DAC having the same frequency as the clock CK.
Simultaneously, the read-out control circuit 14 delivers a control signal S which controls a switching section 9 so that the primary color signals can be switched in the sequence of the primary colors R, G and B, for example. In response to the signals 3H and 3V, the coloring control circuit 15 delivers a coloring control signal CS. Also, in response to the signals 3H and 3V, the shift signal generator circuit 18 delivers a vertical correction pulse SS, and the display control circuit 16 delivers a horizontal sync signal having a triple rate 3HD (i.e., HS) and a vertical sync signal having a triple rate 3VD (i.e., VS). Using these outputs from the controller 19, the field sequential signal generator 1 is controlled to deliver three signals of one field in succession.
In the conventional system mentioned above, a different picture can not be delivered every field. If it is attempted to deliver a different picture every field, a memory having nearly double capacity is required, increasing the cost. To avoid such the increase of cost, the same picture of one field is displayed three times in succession to achieve this, and the switching section 9 sequentially switches the picture signal in the original sequence of the primary colors R, G and B at an interval which is equal to one-third the interval between adjacent vertical sync signals VD's of the original signal. They are sequentially delivered as the signals for one field. Such control is performed by the RGB selection signal S from the controller 19. An output from the switching section 9 is fed, as the field sequential signal RGB, to the monochromatic picture display device 4 where the picture is displayed on the basis of the field sequential signal RGB. At this time, the scanning due to the vertical and the horizontal deflection takes place at the triple rate as compared with the scanning rate occurring in the conventional system.
Referring to FIG. 26, the deflection control circuit 22 includes the horizontal deflection circuit 25 and the vertical deflection circuit 24, each of which operates to deliver the horizontal deflection pulse HP and the vertical deflection pulse VP, respectively, which are "saw-tooth" pulses acting to deflect the electron beam in the CRT 21, on the basis of the triple rate horizontal sync signal 3HD and the triple rate vertical sync signal 3VD. In response to the vertical correction pulse SS delivered from the vertical deflection shift circuit 23, the vertical deflection circuit 24 shifts the vertical deflection pulse VP up and down. Subsequently, light from the monochromatic picture displayed on the CRT 21 is passed through the coloring device 5 having the rotary color filter 28. It is to be understood that the rotary color filter 28 may be replaced by liquid crystal shutter or the like.
A signal which is displayed on the CRT usually includes an interlaced signal such as an NTSC signal, and non-interlaced signal such as a signal from a personal computer. As shown in FIG. 28, the interlaced signal forms one picture frame with two fields. Since the number of horizontal sync signals contained in the vertical sync period includes a fraction equal to 0.5, two picture frames which are vertically displaced are sequentially displayed, thus deceiving a viewer and enhancing the vertical resolution. In the prior art system mentioned above, such an interlaced signal is converted into a field sequential signal RGB for display. At this end, the deflection control circuit 22 delivers the vertical deflection pulse VP and the horizontal deflection pulse HP on the basis of the vertical control signal VS (3VD) and the horizontal control signal HS (3HD). Since each of the vertical and horizontal deflection pulses VP and HP has a triple period as compared with the sync signals HD and VD, a picture of each color is interlace scanned every one-third field.
However, as illustrated in FIG. 30, there occurs a problem that the position of the scanning lines is shifted vertically without a vertical correction or in the absence of the vertical correction pulse SS. Specifically, without the vertical correction or in the absence of the vertical correction pulse SS, the vertical deflection pulses will be in the form of triangular waveforms having an equal spacing as illustrated in FIG. 31, but the field sequential signal will be lagging or leading (refer "G" in the field sequential signal shown in FIG. 31), whereby the position of scanning lines in the picture being displayed is displaced vertically. When employing the monochromatic picture based on the field sequential signal RGB, the color synthesis in the eye cannot be properly achieved unless different primary color signals are displayed on the same position on the display screen. Otherwise there results a picture containing color breakup and having a degraded vertical resolution.
To overcome such problem, there has been a proposal to utilize a vertical correction pulse SS, which is added as an offset voltage (or current) to the vertical deflection pulse to displace the position of the scanning lines up or down, so that if the same field is delivered in succession, a mismatch between the position of the scanning lines during the individual fields can be prevented, as shown in FIG. 32 and FIG. 33. In this instance, the vertical deflection pulse is shifted either up or down as shown in FIG. 33, whereby the scanning line assumes the same position during the individual fields, permitting a display in which a degradation in the vertical resolution is minimized.
However, when this approach is employed, there is a need to provide a shift signal generator circuit for generating a vertical correction pulse in order to prevent a color breakup or to increase the vertical resolution when displaying an interlace scanning picture signal, presenting a problem that the resulting arrangement becomes expensive.
When the vertical deflection takes place under the influence of an electric field, and the deflection control circuit 22 is capacitively coupled to the monochrome CRT 21 through a capacitor as shown in FIG. 34, the vertical deflection pulse VP will be averaged. Accordingly, if the vertical correction pulse SS is applied, there remains a mismatch of positions of scanning lines in the interlace scanning display. Considering the reason here for, it will be noted that the vertical deflection circuit 24 is constructed in a manner as shown in FIG. 35, and delivers a triangular waveform by closing a switch 33 in response to a vertical control signal VS to charge a capacitor 34 from a constant current source 31 during a scan interval while the charge stored is discharged from the capacitor 34 during a blanking period. At this time, the waveform of the vertical deflection pulse VP is averaged as illustrated in FIG. 36. Accordingly, the position of the scanning line can not be properly corrected for each field, but a picture of each field is displaced while being slightly offset from each other.
In the prior art system as mentioned above, a picture is displayed on the basis of the field sequential signal at a triple rate, as compared with the usual arrangement. Accordingly, the spacing of the horizontal and the vertical sync signal will be one-third the usual value. This means that a blanking interval which is provided for the flyback of the electron beam is reduced, and as a consequence, the flyback cannot be achieved in a satisfactory manner, and the flyback operation extends into active display interval, presenting a problem that light from the flyback portion appears on the display screen. To eliminate such problem, it has been necessary to narrow the effective screen size which can be used for the display.
In addition, when the rotary color filter 28 is used to color the picture being displayed, each color filter section is capable of transmitting on the order of only 20% of the white light which is emitted from the monochrome CRT 21, presenting a problem of insufficient luminance.